{"id":"CVE-2026-90124","published":"2026-09-17T17:17:04.650","lastModified":"2026-09-17T17:17:04.650","description":"In the Linux kernel, the following vulnerability has been resolved:\n\nirqchip/renesas-rzg2l: Fix loss of interrupt\n\nrzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a\nread-modify-write on the ISCR/TSCR status registers to clear the bit\nfor the interrupt just handled. Since these registers are\nwrite-0-to-clear per bit, this is racy:\n\nIf another interrupt's status bit gets set between the read and the write,\nthat bit is written back as 0 by the software-constructed value, clearing\nan interrupt that hasn't been serviced yet and losing it.\n\nThis can be reproduced by triggering multiple interrupts at once, e.g.:\n\n  gpioset -c gpiochip0 355=0 353=0 328=0 352=0\n\nFix this by writing back only the bit being cleared, with all other bits\nset to 1, instead of read-modify-writing the whole register.  Since 1-bits\nare left unchanged by hardware, concurrently-set status bits for other\ninterrupts are preserved.","cvssScore":null,"cvssSeverity":null,"cvssVector":null,"cwes":[],"vendors":[],"products":[],"references":[{"url":"https://git.kernel.org/stable/c/3791e242ec2e5a5cd9e010a75ed1125d0e84d394","tags":[]},{"url":"https://git.kernel.org/stable/c/38c6831fefde0ff89f8d2dcb924f957a89dec414","tags":[]},{"url":"https://git.kernel.org/stable/c/50b10bd0c2d721ad38abd1abe3acdefb6caa0944","tags":[]},{"url":"https://git.kernel.org/stable/c/b5ba8b861b5d833394bd23df3f4b59883ef18c88","tags":[]},{"url":"https://git.kernel.org/stable/c/c043591f03a8111f7d306b8122c444a949486269","tags":[]},{"url":"https://git.kernel.org/stable/c/dbecbe23dc606c4af68b4591a41124186f5c1802","tags":[]}],"exploitRefs":[],"hasPoc":false,"ai":null}